1. Technical Field
The present invention relates to a semiconductor memory device having an echo clock path, and more particularly, to a semiconductor memory device capable of preventing skew between output data and an echo clock by controlling the generation of the echo clock.
2. Description of Related Art
When a synchronous pipe line type semiconductor memory device receives/outputs data from/to an external central processing unit (CPU), it will output an echo clock as a reference signal. A device such as an external CPU, fetching data from a semiconductor memory device, senses output time of data from the semiconductor memory device depending on power source, temperature, etc., through such an echo clock. Thus, the device can fetch and use correct data irrespective of environmental changes.
Most memory devices output an echo clock only at a read operation mode. However, double data rate SRAMs (DDR SRAMs), for example, output an echo clock both at a read operation mode and at a write operation mode. This is a free running echo clock mode. The mode uses the main data lines (MDL) for an echo clock connected to a power source voltage (VDD) or a ground voltage (GND) (as opposed to sensing the main data lines (MDL) for output data developed just after data are output through a sense amplifier), because the main data line (MDL) is potential-developed only at a read operation.
However, the free running echo clock mode has a disadvantage in that skew between the output data and the echo clock increases at a limit region of an operation cycle of a semiconductor memory device. To solve the problem, conventional semiconductor devices have employed a fuse for delaying an output clock generated from a data output clock driver to decrease the skew between a clock out (CQ) and a data out (DQ).
FIG. 1 is a block diagram of a conventional semiconductor memory device having an echo clock path. The semiconductor memory device comprises a cell data output part 10 for sensing and amplifying data in a memory cell array 20, synchronizing the amplified data with a data enable clock KDATA and outputting the synchronized data to an external input/output pad (not shown); an echo clock generator 12 synchronized with the data enable clock signal KDATA and receiving a power source voltage VDD and a ground voltage GND and generating an echo clock; an output data clock driver 14 synchronized with a rising edge and a falling edge provided from an external signal and generating the data enable clock KDATA; a variable delayer 16 having a plurality of delay paths, each delay path delaying the data enable clock KDATA differently and selecting a delay path in response to a delay path select signal to supply the delayed data enable clock KDATA to the cell data output part 10 and the echo clock generator 12; and a fuse array 18 having a plurality of fuses and providing the delay path select signal to the variable delayer 16.
The cell data output part 10 comprises a memory cell array 20 having a plurality of memory cells; main data lines MDL_T (Main Data Line_True) and MDL_C (Main Data Line_Complement) for receiving sensed and amplified data from the memory cell array 20; a data latch 22 for latching signals loaded on the main data line (MDL_T and MDL_C); a data output buffer 24 buffering an output data of the data latch 22 in response to the data enable clock KDATA; and an off-chip driver 26 for outputting the buffered data to an external input/output pad (not shown).
The echo clock generator 12 comprises an echo clock latch 28, connected to the power source voltage VDD and the ground voltage GND, for latching the voltages as echo data; a data output buffer 30 for buffering an output data of the data latch 28 in response to the data enable clock KDATA; and an off-chip driver 32 for outputting the buffered echo data to an external input/output pad (not shown).
Referring FIG. 1, when data is sensed and amplified in the memory cell array 20, the data is loaded on the main data line (MDL_T and MDL_C). The data latch 22 latches the loaded data and supplies the latched data to the data output buffer 24. At this time, the echo clock latch 28 latches the power source voltage VDD and the ground voltage GND and supplies the latched voltages to the data output buffer 30.
The output data clock driver 14 produces the data enable clock KDATA in response to a rising edge and a falling edge of an external signal and supplies the data enable clock KDATA to the variable delayer 16. The variable delayer 16 provides a plurality of delay paths, each having a path delayer. The output of each path delayer is selectively supplied to the data output buffers 24, 30 in the data output part 10 and the echo clock generator 12 by a delay select signal output from the fuse array 18, respectively. For example, the variable delayer 16 may have a plurality of inverters serially connected to each other.
The fuse array 18 has at least two or more fuses connected between the power source voltage VDD and the ground voltage GND, and generates the delay select signal corresponding to selective cutting of the fuses, to provide the delay select signal to the variable delayer 16. The fuses are selectively cut in response to operational frequencies of the memory device. Accordingly, the delayed data enable clock KDATA is input to the data buffers 24, 30 in response to the operation cycle. The data output buffers 24, 30 output data and the echo clock from the memory cell array 10 and the echo clock latch 28 to the off-chip drivers 26, 32 in response to the delayed data enable clock KDATA, respectively. The off-chip drivers 26, 32 output the data and echo clock through an external data input/output pad and an external echo clock pad, respectively.
In the conventional device shown in FIG. 1, the skew between the Data Out and the Echo Clock is reduced by delaying an output clock for a predetermined time in a operation cycle. But, there is a problem that the frequency range of the DDR SRAM is limited because the delay time of output clock cannot be controlled after the SRAM is packaged.
FIG. 2 shows a block diagram of a semiconductor memory device having a dummy SRAM cell. The dummy SRAM cell compares a clock signal with output data, and reduces the delay of the output clock in a long cycle time. A cell data output part 10 comprises a dummy cell array 34 in addition to a memory cell array 20. The dummy cell array 34 senses and amplifies data of dummy cell to output the amplified data to dummy main data lines DMDL_T (Dummy Main Data Line_True) and DMDL_C (Dummy Main Data Line_Complement). A data to clock comparator 36 receives the data on the dummy main data lines (DMDL_T and DMDL_C), and compares the data with a data enable clock KDATA. A register 38 receives a comparison data from the data to clock comparator 36 and selects a delay select signal corresponding to the comparison data to output the delay select signal to a variable delayer 16. The variable delayer 16 selects a delay path corresponding to the delay select signal and provides the delayed data enable clock KDATA to the data output buffers 24, 30 in the cell data output part 10 and the echo clock generator 12, respectively.
This conventional device has a disadvantage in that additional hardware is required because of repeating the path from the dummy cell array to an output latch, while controlling clock delay irrespective of a cycle time.
To solve the problems as described above, it is an object of the present invention to provide a semiconductor memory device effectively capable of removing skew between data output from a memory cell and an echo clock output from an echo clock generator.
It is another object of the present invention to provide a semiconductor memory device capable of selecting an optimal delay time in an operation cycle time even after packaging.
According to an aspect of the present invention, a semiconductor memory device comprises a data output circuit for sensing and amplifying data in a memory cell array and for synchronizing the amplified data with a data enable clock signal to output the data; an echo clock generator synchronized with the data enable clock signal and receiving a power source voltage and a ground voltage to generate an echo clock; a delay circuit comprising a plurality of delay paths, wherein each delay path delays the data enable clock by different time, and wherein the delay circuit selects a delay path of the plurality of delay paths in response to a delay path select signal to supply the delayed data enable clock to the data output circuit and the echo clock generator; a test controller for generating a mode select signal and a delay path test signal in response to a test code signal; and a delay signal selection circuit comprising a plurality of fuses for producing a default delay path select signal based on a programmed state of the plurality of fuses, and a multiplexer, responsive to the mode select signal, for selectively providing the default delay path select signal or the delay path test signal to the delay circuit.
The device may further comprise an output data clock drivers synchronized with a rising edge and a falling edge of an external signal to generate the data enable clock.
In one embodiment of the present invention, the delay circuit comprises a plurality of delay devices serially connected to input node of the data enable clock and a plurality of switches, in which at least one switch is connected to the input node of the data enable clock or the output of a delay device. The switches are selectively activated in response to the delay path select signal to output a non-delayed data enable clock signal or delayed data enable clock signal.
In one embodiment of the present invention, the delay signal selection circuit further comprises a first transistor, connected between the plurality of fuses and the ground voltage, for reading the programmed state of the fuses in response to a control signal, and a latch, connected between the plurality of fuses and the first transistor, for latching the default delay path select signal output from the plurality of fuses. The multiplexer receives the default delay path select signal from the latch and receives the delay path test signal and the mode select signal from the test controller. And, the multiplexer selects the delay path test signal as the delay path select signal when the mode select signal is active, and selects the default delay path select signal as the delay path select signal when the mode select signal is inactive.
According to another aspect of the present invention, a method is provided for preventing skew between output data and echo clock in a semiconductor memory device. The method comprises the steps of: generating a data enable clock signal; and delaying the data enable clock signal by an amount of delay time that reduces skew between an output data signal and an echo data signal, wherein the step of delaying comprises selecting between one of a default control signal to delay the data enable signal by a predetermined amount and a test control signal to dynamically modify an amount of delay of the data enable signal during a test mode.
According to further aspect of the present invention, a semiconductor device comprises means for generating a data enable clock signal; means for generating a default control signal to delay the data enable signal by a predetermined amount; means for selecting one of the default control signal and a test control signal to dynamically modify an amount of delay of the data enable signal during a test mode; and means for delaying the data enable clock signal by an amount of delay time that reduces skew between an output data signal and an echo data signal in response to the selected signal.